Semiconductor devices and quantum transport devices have revolutionized the electronics industry and made possible the fabrication of digital logic circuits with ever-decreasing device count, power usage, and circuit complexity. Such devices are typically formed from a number of discrete material layers of various metals, insulators, and semiconductors, and are often doped with specific impurities to adjust their electronic properties as desired. These layers are usually very thin, with thicknesses on the order of 500-3000 Å. As these devices become smaller, and the layers thinner, their response time decreases as well. For instance, devices based on resonant tunneling effects can exhibit intrinsic response times in the sub-picosecond range. Tunneling is an inherently fast physical process and to date, resonant tunneling diodes (RTDs) are the fastest solid-state devices reported.
To overcome problems associated with diode-based digital circuits, RTD circuits have been integrated with high electron mobility transistors (HEMTS) or heterojunction bipolar transistors (HBTs), which have resulted in increasingly complex material growth processes. Other efforts have been dedicated to developing unipolar and bipolar resonant tunneling transistors (RTTs). Recent RTTs employ closed coupled quantum wells in Si or GaAs. U.S. Pat. No. 6,080,995 to Nomoto, for instance, discloses such a quantum device functioning as a memory device, wherein application of a voltage to a gate electrode allows electrons to tunnel from a first to a second quantum well and accumulate therein, thereby indicating a change in state of the device.
The fabrication of such devices is not a trivial matter, and complexity increases while manufacturing yield decreases as the devices become smaller. U.S. Pat. No. 6,110,393 to Simmons et al, for instance, discloses an epoxybond-and-stop-etch (EBASE) method for fabricating a double electron layer tunneling (DELTT) device wherein circuit components are grown atop a stop etch layer on a first substrate, and then bonded to a host substrate with a bonding agent. Subsequently the first substrate is etched away while the components are protected by the stop etch layer. This process requires additional backside processing steps to selectively contact each quantum well by boring vias to the emitter and collector contacts. Each of the flip-chip, substrate removal, and backside via forming steps must be carried out within very tight tolerances, and even slight errors can significantly impact fabrication yields. Thus, the suitability of this-process to manufacturing RTT ICs appears to be less that ideal.
What is needed is an improved method for fabricating semiconductor ICs such as RTTs that enable electrically-tunable resonant tunneling between closely coupled channels without a complex backside process, and particularly a method for forming independent contacts to the closely coupled channels. The embodiments of the present disclosure answer these and other needs.